赵潇腾，教授，博士/硕士生导师，华山特聘教授，国家级青年人才。

致力于高速数据接口集成电路研究（如 SerDes，Die-to-Die Interconnection等）。在IEEE JSSC，CICC， RFIC，TCAS-I等高水平期刊及会议发表论文20余篇，具有软件著作权一项，拥有专利数项。主持国家自然科学基金项目2项，包括面上项目一项；参与科技部重点研发计划 1 项。

科研亮点工作

■ 2022年获澳门特别行政区研究生科技研发奖（每两年1次）。

■所设计的无参考时钟与数据恢复电路入选2022年“中国半导体十大研究进展候选”。

■2019年以第一作者获IEEE APCCAS最佳论文奖（唯一篇），

■2021年以第一作者获IEEE RFIC最佳学生论文奖（3rd Place）

招生研究方向

博士研究生：集成电路科学与工程

学术硕士研究生：集成电路科学与工程

专业硕士研究生：电子信息

欢迎有志于从事高速数据接口集成电路研究的同学报考

近期科研成果（部分）

[1]Zhicheng Dong, Shubin Liu*,Xiaoteng Zhao*, Baotian Hao, Xianting Su, Hongzhi Liang, Menghao Wang and Zhangming Zhu, " A 0.08-%/V 32.3-ppm/°C 36.6-kHz Unregulated Current-Reuse Ring Oscillator with VGS-Ratio Based Compensation Using One-Type-Only Resistor."IEEE Journal of Solid-State Circuits, vol. XX, no. XX, pp. XXXX -XXXX, XX 2024.(Accepted)

[2]Xiaoteng Zhao, Yong Chen, Lin Wang, Pui-In Mak, Franco Maloberti, and Rui P. Martins, “A sub-0.25pJ/bit 47.6-to-58.8Gb/s reference-less FD-less single-loop PAM-4 bang-bang CDR with a deliberate-current-mismatch frequency acquisition technique in 28nm CMOS,”IEEE Journal of Solid-State Circuits, vol. 57, no. 5, pp. 1358-1371, May 2022.[Invited Paper of RFIC Special Issue]

[3]Xiaoteng Zhao, Yong Chen, Pui-In Mak, and R. P. Martins, "A 0.0285-mm² 0.68-pJ/bit single-loop full-rate bang-bang CDR without reference and separate FD pulling off an 8.2-Gb/s/μs acquisition speed of the PAM-4 input in 28-nm CMOS,"IEEE Journal of Solid-State Circuits, vol. 57, no. 2, pp. 546-561, Feb. 2022.

[4]Xiaoteng Zhao, Yong Chen, Lin Wang, Pui-In Mak, Franco Maloberti, and Rui P. Martins, "A sub-0.25pJ/bit 47.6-to-58.8Gb/s reference-less FD-less single-loop PAM-4 bang-bang CDR with a deliberately-current-mismatch frequency acquisition technique in 28nm CMOS"IEEE Radio Frequency Integrated Circuits Symposium (RFIC), Atlanta, GA, USA, pp. 131-134, Jun. 2021. (Best Student Paper Award, 3rd Place)

[5]Xiaoteng Zhao, Yong Chen, Pui-In Mak, and Rui P. Martins, “A 0.14-to-0.29-pJ/bit 14-GBaud/s Trimodal (NRZ/PAM-4/PAM-8) Half-Rate Bang-Bang Clock and Data Recovery Circuit (BBCDR) in 28-nm CMOS”IEEE Asia Pacific Conference on Circuits and Systems (APCCAS), Bangkok, Thailand, pp. 229-232 Nov. 2019.(Best Paper Award, 1 of 105 papers)

[6]Xiaoteng Zhao, Yong Chen, Pui-In Mak, and Rui P. Martins, "A 0.0285mm²0.68pJ/bit single-loop full-rate bang-bang CDR without reference and separate frequency detector achieving an 8.2(Gb/s)/µs acquisition speed of PAM-4 data in 28nm CMOS,"IEEE Custom Integrated Circuits Conference (CICC), Boston, MA, USA, pp. 1-4, Mar. 2020.

[7]Xiaoteng Zhao, Yong Chen, Pui-In Mak, and Rui P. Martins, "A 0.14-to-0.29-pJ/bit 14-GBaud/s trimodal (NRZ/PAM-4/PAM-8) half-rate bang-bang clock and data recovery (BBCDR) circuit in 28-nm CMOS,"IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 68, no. 1, pp. 89-102, Jan. 2021. (Invited paper)

[8]Xiaoteng Zhao, Yong Chen, Pui-In Mak, and Rui P. Martins, "A 0.0018-mm²153% locking-range CML-based divider-by-2 with tunable self-resonant frequency using an auxiliary negative-g_mcell,"IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 66, no. 9, pp. 3330-3339, Sep. 2019.

[9]Xiaoteng Zhao, Yong Chen, Xuqaing Zheng, Pui-In Mak, and Rui P. Martins, "A 0.01-mm²1.2-pJ/bit 6.4-to-8Gb/s reference-less FD-Less BBCDR using a deliberately-clock-selected strobe point based on a 2π/3-interval phase "IEEE MTT-S International Microwave Symposium (IMS), Atlanta, GA, USA, pp. 386-389, Jun. 2021.

[10]Zhicheng Dong, Shubin Liu,Xiaoteng Zhao,Baotian Hao, Hongzhi Liang, Haolin Han, Menghao Wang, Weijie Han, and Zhangming Zhu, "A 0.012mm²36.41kHz Temperature-Insensitive Current-Reuse Ring Oscillator Achieving 0.077%/V Line Sensitivity across a 1.3V-to-3.7V Unregulated Supply,"IEEE Custom Integrated Circuits Conference (CICC), San Antonio, TX, USA, pp. 1-2, Apr. 2023.

[11]Zhicheng Dong,Xiaoteng Zhao*, Weitan Huang, Yuan Gao, Shubin Liu, Lihong Yang, and Zhangming Zhu, "A 30.5-to-31 GHz Sampling PLL With Double-Edge Sampling PD and Implict Common-Mode VCO Scoring 39.69-fs RMS Jitter and -253.6-dB FoM in a 0.047mm2 Area" IEEE ISCAS, 2024(Accepted).

[12]Shubin Liu, Zhicheng Dong, Menghao Wang,Xiaoteng Zhao*, Chenxi Han, Xianting Su, and Zhangming Zhu, " A 4-26 Gbaud Configurable Multi-Mode Non-Uniform EOM with Improved Twin PI for High-Speed Wireline Communication Achieving 3-μs EW/EH Evaluation and 0.99-R²Accuracy."IEEE Radio Frequency Integrated Circuits Symposium (RFIC)2024(Accepted).

[13]Lin Wang, Yong Chen, Chaowei Yang,Xiaoteng Zhao, Pui-In Mak, Franco Maloberti, and Rui P. Martins, "A 10.8-to-37.4 Gb/s Reference-Less FD-Less Single-Loop Quarter-Rate Bang-Bang Clock and Data Recovery Employing Deliberate-Current-Mismatch Wide-Frequency-Acquisition Technique,"IEEE Transactions on Circuits and Systems I: Regular Papers, vol. 70, no. 7, pp. 2637-2650, Jul. 2023.

隶属于 模拟集成电路与系统教育部重点实验室

实验室主任：朱樟明教授, 国家自然科学基金创新研究群体牵头人（2020）、国家杰出青年科学基金（2016）、教育部特聘教授（2018）、国家WR领军人才（2017）、中国教师发展基金委首届卓越青年研究生导师奖励基金（2023）、国家优秀青年科学基金（2013）、教育部新世纪优秀人才
https://aics.xidian.edu.cn/xwgg/xwdt.htm