A 0.0285-mm² 0.68-pJ/bit single-loop full-rate bang-bang CDR without reference and separate FD pulling off an 8.2-Gb/s/μs acquisition speed of the PAM-4 input in 28-nm CMOS
Date of Publication:2023-12-27Hits:
- Journal:IEEE Journal of Solid-State Circuits
- Place of Publication:USA
- Key Words:Acquisition speed, BBCDR, charge pump CP, CMOS, PAM4, FD, HCC,JTOL, JTF, PD, SP
- Abstract:This article reports a single-loop full-rate bang-bang clock and data recovery (BBCDR) circuit supporting a fourlevel pulse amplitude modulation (PAM-4) pattern. We eliminate both the reference and the separate frequency detector (FD) by deliberately adding two fixed strobe points in the bang-bang phase detector (BBPD) curve via a clock-selection scheme. As such, we can achieve a wide frequency-capture range in a single-sided FD polarity. The BBPD also incorporates a hybrid control circuit to automate the frequency acquisition over a wide
frequency range.
- Indexed by:Journal paper
- Volume:57
- Issue:2
- Page Number:546-561
- Translation or Not:no
